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Existing non-invasive lung cancer diagnostic equipment has difficulty in detecting early stage lung cancer as abnormal tissue is smaller than 0.5cm in size. According to studies showing that volatile organic compounds (VOCs) from human breath gas can provide biomarkers for human disease, especially for lung cancer [1], a non-invasive method was developed to measure the exhaled air from cancer patients...
A wide-tuning-range and low-phase-noise LC voltage controlled oscillator (VCO) is presented in this paper. With the variable current source and source damping resistor, the proposed VCO exhibits a phase noise of −115dBc/Hz at 1MHz offset from 6 GHz carrier, and a power dissipation of 1.4mW. In addition, its tuning range is from 4.9 to 6.9 GHz with the MIM capacitor bank and differentially controlled...
A half-rate 4-tap decision feedback equalizer (DFE) is implemented in 0.13µm CMOS technology for low-power I/O links. Modified current-mode logic (CML) latches with PMOS loads are used in the new proposed DFE to achieve better power and area efficiency. The proposed DFE consumes only 1.914mW from a 1.2V supply when equalizing 6.25Gb/s data passing through a simulated low-pass channel with 18 dB of...
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 ??m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25 MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7 dB, which is 16.6-bit resolution, 103 dB dynamic range. The whole circuits consume 58.55-mW from a single...
Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. This paper presented a new dynamic circuit scheme, which could achieve higher noise margin without sacrificing much power consumption and delay time. This design achieves a higher noise...
An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.
A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage...
A novel circuit of mixed-voltage I/O buffer is proposed in this work. The new buffer uses NMOS driver transistors instead of PMOS-driver, which is commonly used in the prior designs. With the help of a bootstrapped circuit, the buffer is free of the threshold voltage loss problem originated from NMOS driver. The proposed buffer can overcome the problem of leakage current paths and gate-oxide reliability...
A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits...
A fully integrated LNA suitable for ultra-low-voltage and ultra-low-power applications is designed in 0.13 mum CMOS technology. A two-stage common-source configuration and forward-body-bias MOSFET are employed to reduce the supply voltage. The proposed LNA exhibits 14.3dB power gain and 2.93dB noise figure at 5GHz while consuming only 0.64mW DC power at the ultra-low supply voltage of 0.4V
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