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The next-generation enterprise Xeon® processor consists of 10 Westmere 32nm cores and a shared inclusive L3 cache (LLC) integrated on a monolith ic die, with link-based l/Os. This paper focuses on the innovations and circuit optimizations over the predecessor targeting idle power reduction, robust high-speed I/O links, and performance per watt improvements. The processor is implemented in 32nm CMOS...
An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused...
An on-die multi-core circuit-switched network achieves 2.64Tb/s throughput for an 8??8 2D mesh, consuming 4.73W in 45nm CMOS at 1.1V and 50??C. Pipelined circuit-switched transmission, circuit channel queue circuits and dual supplies enable up to 1.51Tb/s/W energy efficiency, with scalable streaming performance of 6.43Tb/s.
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is through silicon via...
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