The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper investigates memristor based demodulators and proposes new circuit designs for Binary Frequency Shift Keying (BFSK) and circular 8-Quadrature Amplitude Modulation (QAM) demodulators using two memristors at most. The proposed designs consider utilizing the unique features of the memristor element, crucially, its variable average memristance with the amplitude, phase and frequency of the...
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents...
Decimal floating-point addition is important for financial and business applications. There has been a growing interest in implementing decimal floating-point adders in hardware to enhance the speed of the decimal floating-point operations. In this paper, a redundant decimal floating-point adder is proposed with the ultimate objective of enhancing the speed of the decimal floating-point addition....
Decimal floating-point designs require a verification process to prove that the design is in compliance with the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754-2008). Our work represents three engines, the first engine for the verification of decimal addition-subtraction operation, the second for the verification of decimal multiplication operation, and the third for the verification of...
An architecture for the computation of a decimal powering function is presented in this paper. The algorithm consists of a sequence of overlapped operations: 1) digit recurrence logarithm, 2) sequential multiplication, and 3) on-line antilogarithm. A correction scheme is introduced between the overlapped operations to guarantee correct on-line calculations. Execution times are estimated for decimal64...
This paper proposes an area efficient, low energy, high speed pipelined architecture for a Reed-Solomon decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t Finite Field Multipliers (FFMs) is used to calculate the error locator and evaluator polynomials to...
This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit performing the operation ± (A × B) ± C on decimal floating-point operands. The proposed design is fully compliant with the IEEE 754-2008 standard and supports the two standard formats decimal64 and decimal128. Furthermore, the proposed design may be controlled to perform the multiplication...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.