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Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents...
An architecture for the computation of a decimal powering function is presented in this paper. The algorithm consists of a sequence of overlapped operations: 1) digit recurrence logarithm, 2) sequential multiplication, and 3) on-line antilogarithm. A correction scheme is introduced between the overlapped operations to guarantee correct on-line calculations. Execution times are estimated for decimal64...
This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit performing the operation ± (A × B) ± C on decimal floating-point operands. The proposed design is fully compliant with the IEEE 754-2008 standard and supports the two standard formats decimal64 and decimal128. Furthermore, the proposed design may be controlled to perform the multiplication...
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work...
Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a fully parallel Decimal64 floating point (FP) multiplier compliant to IEEE Std 754-2008 for floating point arithmetic. The proposed multiplier possesses novel methods to target low latency. The proposed design...
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