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This paper presents a switched-capacitor DeltaSigma analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3-1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped...
The requirements of next-generation wireless terminals are driving RFIC design toward ubiquitous multistandard connectivity at reduced power consumption and cost. While the use of scaled CMOS technology is required to allow economically feasible single-chip integration with a digital processor a software-defined radio (SDR) is the preferred approach to provide a reconfigurable platform, that covers...
This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. The methodology is to take a data-mining perspective on a Pareto Optimal Set of sized analog circuit topologies, then doing: extraction...
Fully integrated Systems-On-Chip demand very accurate, low power, temperature independent clock references. In this paper, an improved Wienbridge topology is presented, meeting the specifications of this problem. Measurements show a temperature dependence of 86 ppm/degC and absolute accuracy of 0:9% at an oscillation frequency of 6 MHz. The circuit consumes 66 muW and is realized in a 65 nm technology...
This paper presents the design of a local interconnect network (LIN) smart-power driver exhibiting a high degree of immunity against electromagnetic interference (EMI). Improving previous designed architectures, this circuit switches to a low power consumption mode when there is no EMI, while presenting an increased immunity to slope pumping. Measurements illustrate that this proposed LIN driver complies...
An active load which uses positive feedback to achieve an impedance transformation is introduced. The use of this circuit as an active load for a differential amplifier is explored, and it is illustrated with a case study that the output impedance and consequently the voltage gain are improved when this circuit is used.
In this paper a cascade 3-1 feedforward DeltaSigma topology is introduced and compared with other fourth order DeltaSigma ADC's. The third order first loop reduces problems with quantization noise leakage from classical 2-1-1 or 2-2 cascade topologies, leading to lower OTA specifications. Compared to a fourth order single loop converter, more aggressive noise shaping is possible, leading to a lower...
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