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This paper presents a switched-capacitor DeltaSigma analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3-1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped...
This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB...
In this paper a cascade 3-1 feedforward DeltaSigma topology is introduced and compared with other fourth order DeltaSigma ADC's. The third order first loop reduces problems with quantization noise leakage from classical 2-1-1 or 2-2 cascade topologies, leading to lower OTA specifications. Compared to a fourth order single loop converter, more aggressive noise shaping is possible, leading to a lower...
A fully-integrated DC-DC step-up converter in a 0.18 mum 1.8 V CMOS technology is realized with an integrated bondwire spiral inductor and an integrated MIMcap. The converter is designed to generate 3.3 V out of a 1.8 V power supply. Stacked transistors are used to cope with the high voltage. It operates in discontinuous, asynchronous switching mode, with a switching frequency of 100 MHz. The maximum...
This paper presents a switch bootstrapping technique for very high sampling frequencies. The circuit has been implemented in a switched capacitor delta sigma A/D converter operating at 400 MHz in a 0.18 μm CMOS technology. The high sampling frequency allows to use a high oversampling ratio, resulting in a SNR of 53 dB and signal bandwidth of 3.125 MHz with a simple singleloop second order topology...
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