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High-end FPGAs are widely adopted as hardware accelerators, due to their power efficiency, flexibility, and high-performance computing ability. They are, therefore, extremely useful devices for a project with challenges and constraints such as the Square Kilometre Array (SKA). However, the traditional design methods require expert hardware knowledge and long development times for each of the SKA's...
This paper proposes a framework to recognize music emotion, in which an innovative approach to theme extraction is also included. Furthermore, the theme extraction algorithm proposed is based on a fuzzy pattern matching method using a combination of suffix array and dynamic time warping (DTW) algorithm. The classification of music emotion employs an approach of the supervised artificial neural network...
This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell...
A fully-pipelined tile-able 1MB SRAM IP with a 0.127um2 cell in a HKMG 28nm bulk technology has an area of 1.39mm2/MB with 79.2% array efficiency. It operates with 2-cycle latency up to 1GHz. The no-repair hardware has a circuit limited yield of 99.92 and 53% at 100 and 850MHz, respectively with 0.75V VDD. A Data Retention Voltage of 0.42V has been measured.
The algorithm of tracking and localizing a single rapid moving sound target, based on double five-elements-cross arrays, is presented in this paper. The four time-delay-difference values of each array can be estimated by the methods of generalized cross-correlation. And then, the azimuth angle can be calculated with the special structure of the array. The distance between the target and the center...
Network analysis is an essential aspect of spatial analysis; and shortest path analysis holds a leading position in network analysis. This paper, on the basis of Dijkstra-based improved algorithm [1], improves data structure by combining hierarchy concept so as to obtain an efficient algorithm with a detailed description of the method. Under VC++6.0 development environment, these two algorithms were...
In a context of high performance low power integrated vision system design, a methodology based on the exploration of many architectural and algorithmic issues, relying on analog pre-processing of low-resolution images, is considered. In this paper we present the algorithm exploration performed for analog coarse motion detection and the corresponding SystemC model developed for coupling with a digital...
A novel self-referenced scheme without reference cell is proposed for 1T1C FRAM, which is a new solution to the access scheme for high density FRAM. It is insensitive and robust to fatigue of the FRAM cells and can overcome the challenges on reference signal design for 1T1C FRAM. Furthermore, the proposed scheme can decrease the power consumption and the die size of 1T1C FRAM, compared with conventional...
We propose a joint multi-camera calibration algorithm based on iterative factorization of the measurement matrix. The matrix is composed of homographies between the model plane and its images. Rescaling and decomposition of the measurement matrix are implemented with series of 3D reconstruction techniques. Since these techniques deal well with the missing data, the model plane disposed in the calibration...
A trimming method for the technological dispersion especially in VLSI array-like analog circuits based on tunnel-effect analogue memory is presented. This trimming can be effected simultenously for a large number of identical elements. By only one common control of trimming to all the elements, the trimming of the dispersion for all the elements in an array circuit is accomplished locally, automatically...
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