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This paper evaluates the benefits of using a high-level synthesis (HLS) tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems. The investigated workflow generates a synthesizable hardware description from a system level C-code along with a set of directives that specify performance criteria such as area utilization and timing closure requirements...
Implementing an algorithm on FPGA is intrinsically more difficult than programming a processor or a GPU. Processor-based implementations “only” require a program to control their pre-synthesized data path, while an FPGA requires that a designer creates a new data path and a new controller for each application. Several approaches have been proposed recently to ease FPGA design. The present work builds...
This paper proposes a generic hardware architecture for runtime acceleration of heterogeneous high performance computing (HPC) clusters. This runtime accelerator performs real time resource allocation and management of HPC systems with low latency on multiple time scales. One of the target applications is to perform the signal processing in wireless communication systems such as LTE and 5G over the...
Some applications, especially real time simulation systems, require to compute a linear system’s solution in a very short amount of time. FPGA are well known to offer low latency computation and current chips are dense enough to implement hundreds of floating point operators. However, their many-stage pipelined architecture and the high cost of the divisors make the implementation of low latency applications...
Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA)...
As the world of computing goes more and more parallel, reconfigurable computing can enable interesting compromises in terms of processing speed and power consumption between CPUs and GPUs. Yet, from a developer's perspective, programming Field-Programmable Gate Arrays to implement application specific processors still represents a significant challenge. In this paper, we present the application of...
The standard way to detect known digital objects inside a stream of bytes consists in using a string matching algorithm initialized with a dictionary containing the objects to detect. Depending on the application, the algorithm may be implemented in software or with dedicated hardware, to speedup the processing. Nevertheless, such approach requires an automaton with a complexity that is linear in...
Hardware-in-the-loop (HIL) simulation is an industrial practice that consists in testing a physical electronic control unit (ECU) against a real-time simulated model of a plant. Typical PWM applications run in the kHz range and can hardly be simulated using standard methods with the typical CPU time-steps that are at best in the 5-10 microseconds range. Migrating the computational load from a CPU...
Large FPGAs require more and more time and expertise to efficiently target custom applications. This paper presents a new methodology based on two configuration levels. At the lowest level, the architecture is fully synthesized, placed and routed by experts to implement a 2-D mesh architecture of configurable algorithmic token machines. At the highest level, the users can program those machines to...
The simulation of electromechanical systems like motor drives often requires sub-microsecond calculation timesteps considering the fast dynamic of such systems and the high-switching frequency involved. Migrating computational load to an FPGA processor has proven to effectively meet the real-time simulation needs of such systems. However, many challenges still must be overcome before broad adoption...
The numerical simulation of power and electromechanical systems necessitates sub-microsecond calculation timesteps if the considered system is characterized by low time constants. Migrating the computational load to an FPGA have shown to suit well the real-time simulation needs of such systems. However, many challenges remain to concretize the broad adoption of FPGA technology for the real-time simulation...
In this paper, we discuss the feasibility of a floating-point accumulator (FPACC) on modern high-end FPGA devices. We explore different implementation scenarios and propose new FPACC architectures for both single and double precision floating-point addends. The proposed strategies can be easily adapted to the implement a multiply-accumulator (FPMAC), with one or two rounding stages, in both single...
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