The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Wafer-level testing allows detection of manufacturing errors and removes non functional devices early in the fabrication process. It is commonly performed by placing a probe card directly above a device under test (DUT) and establishing a mechanical contact between them by means of an array of probes. This is an invasive technique that may damage fragile low-k dielectric layers and deform pads or...
This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and...
This paper presents a 0.45V-to-2.7V level shifter utilizing inductive coupling. Since primary and secondary coils are AC-coupled, each coil can be biased at arbitrary voltage independent from the conversion level difference. This enables both the primary and the secondary circuits to operate at the optimal operating region. In addition, the inductive coupling itself can provide an additional intermediate...
This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.