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We report on aggressively scaled RMG-HKL devices, with tight low-VT distributions [σ(VTsat) ∼ 29mV (PMOS), ∼ 49mV (NMOS) at Lgate∼35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen...
In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors,...
Germanium has emerged as an exciting alternative material for high-performance scaled CMOS, however not without difficulties. After a review of the state-of-the-art, mainly focusing on two techniques to passivate the channel/dielectric interface, we analyze the strengths (carrier mobility, band gap), and weaknesses (n-type doping, lattice mismatch and BTBT leakage) of Ge for MOSFETs. We also identify...
The gamma radiation-induced variation of the transconductance in the subthreshold region is studied for different back-gate voltages and for different kinds of SOI MuGFETs: devices with and without Selective Epitaxial Growth (SEG) and 45° rotated transistors. Wide fin devices show a larger degradation when the back-gate is grounded. The back-channel of narrow fin transistors, on the other hand, needs...
The introduction of high mobility channel materials together with new device structures with improved subthreshold slope provides a pathway into continuing the performance scaling of CMOS technology beyond the classical Si roadmap. The combination of Ge pMOS devices with nMOS devices made on very high electron mobility III/V compounds such as InGaAs can be achieved by selective growth on a Si-wafer,...
We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process...
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