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Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13- SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB)...
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81–86 GHz band was designed and fabricated in 0.13 µm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four...
This paper presents a Ku band Gm boosted Colpitts VCO designed in IBM 0.13µm SiGe BiCMOS8hp technology for E-Band and V-band backhaul transceivers. The VCO achieves 23.3% tuning range, covering 15.2 – 19.2 GHz while maintaining low phase noise. Measured phase noise at 10 MHz is lower than −133 dBc/Hz at 25°C. The VCO shows robust behaviour to temperature variations, with a measured frequency drift...
A high output 1dB compression up-conversion mixer for the entire E band frequency range, 71–76 GHz and 81–86 GHz, is designed and fabricated in IBM 0.13 μm SiGe technology. The mixer is comprised of a double balanced Gilbert cell and a multi-tanh three transistor hybrid transconductance stage, used to enhance the mixer linearity. The conversion gain and output 1dB compression are 3.9dB and +1dBm,...
A Ku band frequency synthesizer is designed and implemented in 0.13μm SiGe technology as a part of an E-band superhetrodyne transceiver chipset. It provides for RF channels of 71–76 GHz in 62.5MHz steps, and features a phase rotating pulse injection division region switching subinteger frequency divider. Output frequency ranges from 15.4 to 16.7 GHz. The measured differential output power is about...
Fully integrated transmitter at E-band frequencies in a superhetrodyne architecture covering the 71–76GHz was designed and fabricated in 0.12µm SiGe technology. The transmitter's front-end includes a power amplifier, image-reject driver, tunable RF attenuator, power detector and IF-to-RF up-converting mixer. A variable gain IF amplifier, quadrature baseband-to-IF modulator, frequency synthesizer and...
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13µm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency...
This paper presents a fully integrated 71–76GHz power amplifiers (PA) fabricated in a 0.12µm SiGe BiCMOS technology. The PA employs five common-emitter stages with on-chip power combining to achieve power gain of 21dB, 17.6dBm output power at 1dB compression, and saturated power of 20.1dBm. The modified Wilkinson combiner that was used shows 0.5dB insertion loss. Small signal characteristics of the...
This paper presents a fully integrated 71–76GHz power amplifiers (PA) fabricated in a 0.12µm SiGe BiCMOS technology. The PA employs five common-emitter stages with on-chip power combining to achieve power gain of 21dB, 17.6dBm output power at 1dB compression, and saturated power of 20.1dBm. The modified Wilkinson combiner that was used shows 0.5dB insertion loss. Small signal characteristics of the...
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency...
This paper demonstrates a frequency multiplier by four (quadrupler) with a cascade topology that exhibits a high conversion gain and high suppression for the 60–77 GHz. Most of the repotted balanced frequency multiplier at mmWave range are frequency doublers, which means that an additional stage have to be used in order to get higher frequency multiplication factor. An additional stage will come at...
An RF receiver front end for EBAND communication in the lower band 71–76GHz frequency range was designed and fabricated in IBM 0.12μm SiGe technology. The LNA composed of four amplification stages, exhibits more than 15dB gain and a NF of less than 6dB in the entire frequency band. A steep two chain stop band filter is used to reject image noise with better than 18dB image rejection. The LNA is followed...
This paper presents a fully integrated 8186GHz power amplifier (PA) fabricated in a 0.12 μm SiGe BiCMOS technology. Three cascode stages, followed by two common-emitter stages were utilized to achieve power gain of 30dB with 12dBm output power at 1dB compression and saturated power of 14dBm. Small signal characteristics show peak gain achieved at 86GHz with both input and output matching is better...
Two sets of E-band transceiver circuits in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13μm SiGe technology. The measured upper band transmitter RF gain chain is 30dB with a saturated output power of 15.2dBm. The LNA exhibits more than 15dB gain. A frequency quadrupler was used to generate the LO signal in both transmitter and...
This paper presents a fully integrated 77GHz power amplifier (PA) fabricated in a 0.13 μm SiGe BiCMOS technology. A 4-stages single ended common-emitter topology was utilized to achieve power gain of 19dB at 77GHz with 14.6dBm output power at 1dB compression, saturated power of 16dBm and 12.5% peak PAE. Small signal characteristics show a wideband behavior - Maximal small signal gain of 23dB achieved...
The paper examines the question of when and how can an on-chip transmission line have a stand-alone, independent model in the actual VLSI design environment. The study addresses a certain set of simple structures, covering most of practical VLSI design needs, which includes coplanar single and coupled structures. Based on theoretical analysis and numerical results, practical criteria of "sufficiently...
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