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Hardware Transactional Memory (HTM) designs must implement conflict detection to guarantee the correctness of transaction execution. A conflict occurs when more than one transaction access the same data and at least one of them attempts to modify the data. The corresponding conflict detection mechanism usually works at a cacheline level that fits naturally into the cache coherence protocol. Thus,...
In Transactional Memory (TM), a conflict occurs when a memory block is accessed concurrently by two or more transactions and at least one of them is a write access. The management of conflicts significantly impacts TM performance. There are two alternative approaches for managing conflicts: Reactive Contention Management (RCM) [1] and Proactive Contention Management (PCM) [2]. Previous contention...
ISI's Advanced Scalable Network Technology (ASNT) project employs multiple specialized network components in an integrated high-performance multicomputer system. Large multicomputer systems are vulnerable to programming error, hardware faults, and potentially, malicious attacks. Allowing direct user access to network interfaces is desirable for performance, but can reduce protection and reliability...
Stacking active layers leads to increased power density and overall higher temperatures in a three dimensional integrated circuit (3DIC). Thermal sensors are therefore crucial for run-time thermal management of 3DICs. A thermal sensor allocation method customized for 3DICs that utilizes ring oscillator based 3D sensors is introduced in this paper. A new 3D thermal map modeling method that facilitates...
In this paper we propose a fast and efficient method of multiobjective optimization for 3DIC building block placement. The objectives are cost, performance and thermal reliability. Our proposed method is based on a Quasi-Newton analytical optimization method. Our approach also uses a scalarization method of Compromise Programming, in which the weighted distance of the objectives from their minimum...
Transactional Memroy (TM) has been proposed as an alternative to locks to simplify parallel programming. While most research has focused on the architectural support of TM, it is at least equally important to investigate the hardware implementation of the key mechanisms of TM to facilitate its deployment in commercial processors. In this paper, we present a light-weight and generic implementation...
Thermal measurement and management is crucial in three dimensional integrated circuits (3DICs) technology because increasing temperature stress is one of the main challenges due to high power density. Because of the physical adjacency and use of Through Silicon Vias (TSVs) as thermal exchangers between the stacked layers, the thermal profiles of the layers are highly correlated with each other. Any...
Hardware Transactional Memory (HTM) systems implement version management and conflict detection in hardware to guarantee that each transaction is atomic and executes in isolation. In general, HTM implementations fall into two categories, namely, eager systems and lazy systems. Lazy systems have been shown to exploit more concurrency from potentially conflicting transactions. However, lazy systems...
Transactional memory has been proposed as an optimistic concurrency-control construct to ease parallel programming. Hardware transactional memory (HTM) approaches implement version management and conflict detection in hardware to guarantee the correctness of transaction execution. Based on the style of version management and conflict detection, state-of-the-art HTM systems fall into two main types,...
Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that often limit performance improvement and power reduction. However, stacking active layers of silicon will lead to increased power density and overall higher temperatures in a 3D chip implementation for many designs. Thermal sensors are therefore crucial for...
In this paper, we investigate and compare the effectiveness of different charge sharing techniques for reduction of charge sharing and collection among adjacent nodes in 65-nm technology NFET transistors. We use Synopsys 2-D TCAD mixed-mode simulations to measure collected charge at a node adjacent to a device struck by a heavy-ion particle for cases of using Shallow Trench Isolation (STI), Deep Trench...
In this paper we use a pair of cross-coupled inverters as a weak-latch to mitigate Single Event Transient (SET) effects in combinational logic for sub-micron technologies. A weak-latch is added to a sequential element input to slow down the data transitions and as a result filters out SET pulses that are faster than its delay. By applying this method we succeed to completely filter out transient pulse...
Hardware signatures have been used for detecting conflicts in Transactional Memory (TM) systems. Even with its area-efficiency, a signature can degrade TM performance by falsely detecting conflicts. Hence, increasing the accuracy of signatures with limited hardware resources is a crucial issue. We propose a simple and efficient signature design, unified signature. Instead of using separate read- and...
Transactional Memory (TM) promises to increase programmer productivity by making it easier to write correct parallel programs. In fulfilling this goal, a TM system should maximize its performance with limited hardware resources. Conflict detection is an essential element for maintaining correctness among concurrent transactions in a TM system. Hardware signatures have been proposed as an area-efficient...
As chip multiprocessors transition from multi-core to many-core, on-chip network power is increasingly becoming a key barrier to scalability. Studies have shown that on-chip networks can consume up to 36% of the total chip power, while analysis of network traffic reveals that for extended periods of execution time, network load is well below the network capacity in many applications. In recent studies,...
Transactional Memory (TM) has attracted considerable attention because it promises to increase programmer productivity by making it easier to write correct parallel programs. To maintain correctness in the face of concurrency, detecting conflicts among simultaneously running transactions is an essential element. Hardware signatures have been proposed as an area-efficient mechanism for conflict detection...
Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Qcrit) required to upset a 6T SRAM cell designed in a commercial 90nm process. We characterize Qcrit using different current models and...
Soft errors are a major reliability concern for today's nanometer technologies. The errors in register files in Application Specific Integrated Circuits (ASIC) can quickly spread to various parts of the system and result in data corruption which may go unnoticed. Single Error Correction (SEC) Hamming code and Triple Modular Redundancy (TMR) provide a high-level mitigation solution for soft errors...
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