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This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise....
This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration...
This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. These can prevent signal dependent offset and reduce the switching network complexity. A 5-bit binary-search ADC applying such proposed techniques has been developed in 65 nm CMOS. It consumes 540 μW under 1V supply voltage at the operating frequency of 600 MS/s. The simulation...
A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 ??W from a 1 V supply...
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