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Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for ???? modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking...
A low-power, low-voltage, single-ended input, four-quadrant CMOS analog multiplier architecture suitable for analog neural network implementations is presented. The architecture takes advantage of the quadratic I-V characteristic of an NMOS and a PMOS transistors both operating in saturation region. Combining NMOS and PMOS transistors allows four-quadrant operation with single-ended input. Due to...
This paper presents design and simulation of two temperature compensated LC Colpitts reference oscillator. First uses an on-chip differential inductor while the other one uses bondwire inductor. Technology is 0.35 mum 2P/4M CMOS technology with high resistivity poly and thick metal option. Oscillator with on-chip differential inductor consumes 7.5 mA from 2.5 V supply and absolute peak frequency deviation...
This paper presents the design of a low-noise amplifier (LNA) with high gain and low noise figure (NF), targeting the X-band, in 0.25 mum SiGe BiCMOS process provided by IHP. Simulation results show that at 10 GHz, the proposed LNA has a noise figure of 2.295 dB, with both input and output impedances matched to 50 Omega, an input return loss of -30.22 dB, an output return loss of -17.02 dB, and a...
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