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The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative...
In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT - BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 μm lithography node with 3.3 V / 5.0 V dual-gate CMOS technology and high-quality passives on a 50 Ω.cm substrate.
High performance communications applications have made technology choices more important than ever. Silicon germanium (SiGe) BiCMOS has enabled the widespread introduction of many these applications by providing superior cost and integration capability, compared to III-V solutions and, relative to RFCMOS, one can attain better time to market. BiCMOS integration approaches for high performance and...
This paper demonstrates latchup results in a 50 Omega-cm substrate wafer in a 0.13-mum technology. Latchup evaluation will evaluate and compare a 10 Omega-cm and a 50 Omega-cm substrate wafer on the NPN bipolar current gain, betanpn, PNP bipolar current gain, betapnp,, the bipolar current gain product, betapnpbetanpn, undershoot, and overshoot phenomena.
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