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A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive...
A processor with 2048 4 b grained processor elements (PE) and a 2 Mb SRAM is implemented in 65 nm CMOS and occupies a 5.29 mm2 die. It achieves 200 MHz operation at 1.0 V and outputs peak power efficiency of 310 GOPS/W. The peak performance reached 191 GOPS at 560 MHz and 1.2 V in the double frequency mode. The processor can be optimized for both power and area by changing the number of PEs from 256...
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and...
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