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A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB...
We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results...
The reliability of Cu and W contacts under high fluence stress mimicking source/drain contacts in the on-state of a transistor is evaluated. We use Kelvin structures to study the contact degradation and to determine the lifetime as a function of voltage and temperature. Failure analysis reveals significant damage created in the proximity of the contacts. It is concluded that not electromigration alone,...
With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location...
In this paper, we investigate the impact of replacing tungsten (W) by a Cu-based contact module. Our experiments show that a 50% reduction in contact resistance can be obtained. This is attributed to both the choice of barrier as well as filling material. An increased drive current is measured on narrow transistors with single contacts. The intrinsic gate oxide reliability is not compromised. Results...
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