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Cell Aware testing (CAT) has received much publicity in recent years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Significant additional fallout...
Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
Open defects in CMOS circuits can cause a gate output to go into a high impedance, or “floating” mode, for some input patterns. Since such defects display (large) delay fault behavior, they are commonly assumed to be covered during structural testing by scan based TDF timing tests. TDF tests are generally applied in the launch-on-capture (LOC) scan test mode to avoid “overtesting” the circuit timing...
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