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Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology...
We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral...
We demonstrate high frequency switching characteristics of TFETs based on the In0.9Ga0.1As/GaAs0.18Sb0.82 material system. These near broken-gap TFETs (NBTFETs) with 200nm channel length exhibit record drive current (ION) of 740μA/μm, intrinsic RF transconductance (GM) of 700μS/μm, and a cut-off frequency (FT) of 19GHz at VDS=0.5V. Numerical simulations calibrated to the experimental data are used...
We demonstrate controlled number and placement of the Ge quantum dot (QD) along with tunnel junction engineering through a self-organized approach for effective management of single electron tunneling. In this approach, a single Ge QD (∼11 nm) self-aligning with nickel-silicide electrodes is realized by thermally oxidizing a SiGe nanorod bridging a 15-nm-wide nanotrench in close proximity to electrodes...
We have developed a simple, manageable, and self-organized manner - thermally oxidizing SiGe nanocavity for precisely controlling Ge quantum dot (QD) number, position, and tunnel path, which is crucial for effective single-electron tunneling devices. The internal structure properties of Ge QDs were systematically characterized. The effectiveness of Ge QD placement is evidenced by high performance...
Precise control on quantum dot (QD) number and tunnel path in a self-organized manner is crucial for effective single electron tunneling. We experimentally demonstrated a single Ge QD (~10 nm) self-aligned with nickel-silicide electrodes via Si3N4/SiO2 tunnel barriers by thermally oxidizing a SiGe nanorod. The fabricated Ge QD single hole transistor (SHT) features with clear differential conductance...
Metal-insulator-semiconductors structures (MIS) with a layer of silicon nanocrystals embedded within two SiO2 layers are fabricated by using plasma enhanced chemical vapor deposition. By using current-voltage (I-V) measurements with different sweep rates, we study the mechanism of electrons and holes charging/discharging characteristic of the MIS structures. Distinct current peaks duo to electrons...
This paper presents performance evaluation of high-kappa/metal gate (HK/MG) process on an industry standard 45 nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45 nm Poly/SiON devices. No additional stress elements were used for this performance gain...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
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