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Parallel-prefix adders draw significant amounts of attention within general-purpose and application-specific architectures because of their logarithmic delay and efficient implementation in VLSI. This paper proposes a scheme to enhance parallel-prefix adders for modulo 2n - 1 addition by incorporating Ling equations into parallel-prefix structures. As opposed to previous research, this work clarifies...
This paper discusses an extension to an open source, variation aware process design kit (PDK), based on scalable CMOS design rules. This PDK is designed for 45 nm feature sizes and is utilized for use in VLSI research, computer architecture, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation...
Although memory is a critical component in general-purpose and application-specific processors, it tends to consume a large amount of power. To alleviate this power dissipation, half-swing memory systems have been proposed which allow memory to be accessed with bitlines that do not swing rail to rail. Unfortunately, half-swing memory systems have additional logic to prevent logic from being written...
Parallel prefix adders draw much attention because of their logarithmic delay. This paper proposes a scheme to enhance parallel prefix adders by incorporating the idea of carry-save addition within the prefix tree. Results are given for several designs using a publicly available nanometer library.
Interest in decimal arithmetic is growing considerably due to its relevance in financial and commercial applications. Previous developments on decimal multiplication focused on sequential implementations due to its complexity. However, recent studies have proposed parallel multipliers to improve performance. This paper clarifies recent techniques for partial product generation and presents implementation...
This paper shows various ways to pipeline popular SRT division algorithms. Different logic gate families and circuit structures are used to explore possible overheads introduced in each implementation. Simulation results are compared to find out the fastest possible architecture and comparisons are explored from parasitically extracted AMI C5N 0.5 mum layouts.
This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm,for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell...
Conventional binary adders have constant energy consumption at constant supply voltage. A large portion of the total energy is typically consumed by the parallel prefix tree, due to high output loads and long wires. This paper presents a multi-mode addition algorithm, which allows a partial shutdown of the prefix tree to achieve lower energy consumption at slower speeds. The algorithm applies to all...
In today's society, decimal arithmetic is growing considerably in importance given its relevance in financial and commercial applications. Decimal calculations on binary hardware significantly impacts performance mainly because most systems utilize software to emulate decimal calculations. On the other hand, the introduction of dedicated decimal hardware promises the ability to improve performance...
Sparse prefix tree adders like carry-select adders and carry-increment adders are commonly used in the implementation of high-speed parallel adders. This paper presents a novel Ling carry-increment adder, which further reduces the area and power consumption as compared to a conventional carry-increment adder. The proposed algorithm utilizes Ling pseudo-carries in both the prefix tree and the output...
Sparse tree adders are a common choice for the implementation of high performance binary addition. However, for constant supply voltage they have constant energy consumption regardless of the operating frequency. This paper presents a dual-mode sparse tree adder that offers a low-speed low-energy mode. This is achieved by disabling the prefix tree in the low-speed mode. Simulation results using extracted...
This paper presents a high-speed method for accurate function approximations of reciprocals. This method employs parallel table lookups followed by multi-operand addition. Similar to previous methods, it takes advantage of leading zeros and symmetry in the table entries to reduce the table sizes. This method, although similar to previous methods, achieves lower memory sizes without having to increase...
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