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With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for evaluation of the state-of-the-art ISP solutions. The proposed comparison...
With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for comparison of state-of-the-art ISP solutions. The effective comparison...
This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips...
Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard...
In this paper, we describe a training environment based on multi-functional software system called “Trainer 1149”. It provides simulation and demonstration functionality for learning, research, and development related to IEEE 1149.1 Boundary Scan (BS) standard. The software supports both the analytic and synthetic learning process. Trainer 1149 is the main component of a recent goJTAG initiative that...
Many contemporary electronic systems are based on such System-on-Chips (SoC) as microcontrollers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that...
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulation than its predecessor SSBDD model. The paper presents...
The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is...
The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesized binary decision diagrams (SSBDD) used for test generation,...
In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical...
Binary decision diagrams (BDD) have become the state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean Functions. For verification, fault simulation and test generation purposes structurally synthesized BDDs (SSBDD) have proved to be better suited than traditional BDDs which represent only the function but not the structure of the circuit. In this paper we present...
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution...
In this work, we propose a multifunctional remote e-learning environment for teaching research by learning and investigating the problems of fault diagnosis in electronic systems. It is a collection of software tools which allow to simulate a system under diagnosis, emulate a pool of different methods and algorithms of fault location, analyze the efficiency of different embedded self-diagnosing architectures,...
A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults. Thanks to the parallelism...
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution...
This paper represents a new iteration, a new look at the problem of microprocessor-based system-level test that takes into account a new reality in semiconductor technologies and electronic manufacturing. We propose a method of testing correct PCB assembly that uses existing debug interface of a microprocessor for test data transfer. Hence, our approach neither has hardware overhead, as in DFT, nor...
LFSR reseeding techniques are often applied in BIST due to their ability to considerably improve the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. The efficiency of a typical reseeding scheme to a large extent depends on the seed selection and consequent test sequence optimization algorithms. This paper proposes a novel efficient reseeding optimization...
Nowadays, test and measurement tasks at high volume production facilities are fully automated. Normally the responses of analog components to test stimuli have to be first digitized before being automatically processed in order to identify deviations from the reference signal. When dealing with high frequency devices, the analog to digital conversion process becomes costly and/or involves data losses...
The efficiency of test generation (quality, speed) for digital systems like microprocessors is highly depending on the methods for diagnostic modeling of systems. For systems with high logic complexity higher level methods are unavoidable.A method is discussed for modeling microprocessors with high level Decision Diagrams (DD). DDs can be used for developing a general theory for diagnosis of systems...
Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability to considerably improve both the fault coverage and...
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