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With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for evaluation of the state-of-the-art ISP solutions. The proposed comparison...
With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for comparison of state-of-the-art ISP solutions. The effective comparison...
We propose a benchmark suite for systematic evaluation of efficiency of new CAD and test algorithms. The suite consists of a set of high performance signal processors. Differently from all other existing benchmark suites, all the member processors of this family perform the same function, but are implemented in different ways, differing mainly in sharing of computing resources. The circuits are characterized...
This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips...
Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard...
In this paper, we describe a training environment based on multi-functional software system called “Trainer 1149”. It provides simulation and demonstration functionality for learning, research, and development related to IEEE 1149.1 Boundary Scan (BS) standard. The software supports both the analytic and synthetic learning process. Trainer 1149 is the main component of a recent goJTAG initiative that...
Many contemporary electronic systems are based on such System-on-Chips (SoC) as microcontrollers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that...
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulation than its predecessor SSBDD model. The paper presents...
Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Fault simulation used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up simulation and to overcome the problem of memory limits in the case of...
In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical...
Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Fault simulation used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up simulation and to overcome the problem of memory limits in the case of...
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution...
A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults. Thanks to the parallelism...
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution...
This paper represents a new iteration, a new look at the problem of microprocessor-based system-level test that takes into account a new reality in semiconductor technologies and electronic manufacturing. We propose a method of testing correct PCB assembly that uses existing debug interface of a microprocessor for test data transfer. Hence, our approach neither has hardware overhead, as in DFT, nor...
This paper presents a method and software for constructing of testabie finite state machines (FSM). The proposed method of impiementing test for FSM has severaf advantages in comparison with common soiutions. However, this method imposes some constraints on FSM synthesis process, which can be satisfied by using specific decomposition technique. The presented software environment (caifed D&S) is...
In this paper, a new hierarchical multi-level technique for malicious fault list generation for evaluating the fault tolerance is presented. For the description of the system three levels are exploited: behavioral, functional signal path and structural gate-network levels, whereas at each level the model of decision diagrams and uniform fault analysis procedures are used. Malicious faults are found...
A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to...
An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. Converting gate-level circuits to the macro-level is accompanied with fault collapsing. A parallel fault analysis algorithm for SSBDDs was developed...
This paper describes an environment for finite state machine decomposition that is developed in Tallinn University of Technology. The presented software called D&S is oriented mostly for demonstration and education purposes, but it can be also used in scientific experiments. Various techniques such as additive, generalized additive and multiplicative decomposition are implemented by different...
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