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In this paper we propose a low-complexity image stitching algorithm. By using the developed algorithm, users can automatically merge images into a panoramic image, even these source images have rotation and zooming actions. We adopt feature-base estimation to get the relation between images and employ down-sampling to reduce computing complexity. We also apply a copy-paste and texture-base scheme...
In this paper, we propose a new algorithm in reversible data hiding, with the application associated with the quick response (QR) codes. QR codes are random patterns, which can be commonly observed on the corner of posters or webpages. The goal of QR codes aims at convenienceoriented applications for mobile phone users. People can use the mobile phone cameras to capture QR code at the corner of web...
Reversible data hiding has been a newly developed branch in data hiding researches. With the definition, when the message is hidden into the original image by some means, the image containing the hidden message is transmitted to the decoder. After decoding, both the original image and the hidden message should both be recovered perfectly. In this paper, we make use of the easily implemented scheme...
This paper presents a new error concealment algorithm, which is suitable for the H.264/AVC coding standard and the hardware implementation. This algorithm can be dividing into two major categories. In the spatial domain, we use the reliable neighboring pixel values with edge detection method to conceal all the lost pixels in the block. In the temporal domain, we propose a variable block size error...
Conventional video surveillance systems often have several shortcomings. First, target detection can't be accurate under the light variation environment. Second, multiple target tracking becomes difficult on a crowd scene. Third, it is difficult to the partition the tracked targets from a merged image blob. Finally, the tracking efficiency and precision are reduced by the inaccurate foreground detection...
This paper presents a high throughput VLSI architecture for H.264/AVC in-loop de-blocking filter (ILF) supporting baseline, main, and high profile (BP/MP/HP) video decoding targeted at HDTV applications. We develop a 4times4/8times8 filter and a buffer management scheme to perform the various coding tools in H.264 de-blocking filter for supporting the coding tools of picture adaptive frame/field (PAFF)...
A 1080 p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mum CMOS technology with an area of 10 mm2 and 242 mW at 145 MHz. Compared to the state-of-the-art design targeted at 720 p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.
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