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For the first time we demonstrate a fully self-contained photonic transceiver system on a single die with monolithically integrated Ge photo-detectors. The transceiver allows error-free bidirectional 4times10 Gb/s WDM transmission using a single CMOS die at each end of the link.
We demonstrate monolithically integrated 4times10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.
We have demonstrated a 40-Gb/s optoelectronic transceiver in a quad small form-factor pluggable (QSFP) module. Each module includes a 4xlO-Gb/s, 0.13 μm CMOS silicon-on-insulator integrated optoelectronic transceiver chip co-packaged with a single, externally modulated CW laser.
A 4-wavelength DWDM optoelectronic transceiver, implemented in a 0.13mum CMOS SOI process, achieves an aggregate rate of 40Gb/s transmission over single fiber. The four channel WDM chip, operating all four Txs and Rxs in WDM configuration consumes -3.5W. This is at nominal operating conditions.
Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic...
We present the world's first optical transmitter monolithically integrated in a CMOS process, achieving 10 Gb/s data modulation rate at 1550 nm with an extinction ratio greater than 6 dB.
An eye-opening monitor circuit in 0.13 /spl mu/m CMOS operates from 1 to 12.5Gbit/s at 1.2V supply. It maps the input eye to a 2D error diagram with 68dB mask error dynamic range. Left and right halt of the eye are monitored separately to capture asymmetric eyes. Tested input amplitude is from 50 to 400mV. The chip consumes 330mW and works at 10Gb/s with a supply voltage as low as 1V.
A new technique for bandwidth enhancement of amplifiers is developed. Adding several passive networks, which can be designed independently, enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known filter component values is...
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