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Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if...
The improvement in security application has lead to the development of hardware cryptography. These crypto-processors are prone to security attack based on observing their power dissipation profile. One of the ways to combat this problem is to introduce randomness in the data. Bus scrambling is one of the ways to introduce non-determinism. But scrambling the data increases the power dissipation on...
Process variations can have a significant impact on both device and interconnect performance in deep submicron (DSM) technologies. In this paper, authors discuss the impact of process parameter variations on bus-encoding schemes for delay minimization. It is shown that if process variability is taken into consideration, there will be a change in effective capacitance (Ceff) of the bus lines because...
In deep sub-micron (DSM) technology, the shrinking wire sizes and bus widths are leading to increased propagation delay of on-chip interconnects. There are various techniques proposed in the literature such as wire shaping, shielding, coding etc. to minimize the delay on bus lines. This paper proposes a new bus-encoding scheme to minimize delay and energy on interconnect lines. The proposed encoding...
Interconnects dominate system performance in DSM (deep sub-micron) domain. In shrinking technologies, propagation delay of on-chip interconnects is becoming a major concern. The present work tries to combine encoding with repeater insertion to reduce the propagation delay in VLSI interconnects. A new coding algorithm for minimizing delay has been proposed which eliminates the cross talk classes 4,...
In CMOS VLSI circuits, the dynamic power dissipation contributes a significant fraction in the overall power dissipation. Hence, the main target of VLSI designers is to minimize the switching activity on the on-chip bus lines. In this paper, the authors propose a novel bus encoding technique which minimizes both self and coupling transition activity to curtail the global power dissipation. The performance...
In deep-submicron (DSM) technology as the wire size is shrinking and the lines are coming closer, the propagation delay of the on-chip interconnects is rapidly increasing. There are various works proposed in the literature such as shielding, coding etc to minimize delay in bus lines. This paper concentrates on minimizing delay on bus lines by suitably encoding the data on the bus. A coding scheme...
In current VLSI technology, interconnects have become the predominant source of power dissipation. Particularly in DSM technology, the spacing between interconnects is very less leading to the dominance of coupling capacitance over self capacitance. In 0.13 mum technology, it has been found that 75% of the power consumption is due to the coupling capacitance whereas only 25% is due to self capacitance...
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