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This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases...
We have investigated Al2O3, Dy2O3, and La2O3 as dielectric cap layers for use in low Vt CMOS integration schemes. The cap layers are found to reduce the Vt by 0.2 V for pFET, and with 0.2 V and 0.5 V for nFET, respectively. Subsequently, we report on the benefits of performing the nitridation (by means of DPN) after cap deposition, instead of before. This allows better control of the nitrogen profile...
The physical and electrical characteristics of high-k (HK) gate dielectric HfLaO were systematically investigated. Incorporation of La in HfO2 can raise the film crystallization temperature from 400degC to 900degC. Moreover, NMOSFETs fabricated with HfLaO gate dielectric exhibit superior electrical performances in terms of threshold voltage (Vth), bias temperature instability (BTI), channel electron...
In this work, by using a novel HfLaO high-kappa (HK) gate dielectric, we show for the first time that with a thermal budget of 1000 degC, Fermi-Pinning in the HK-metal gate (MG) stack can be released. The effective metal work function (EWF) can be tuned by a wide range more than the requirement of bulk CMOSFETs, and also fits the future UTB-SOI CMOSFETs when Si body thickness is approaching 3 nm or...
We report for the first time on the use of a Ni fully germano-silicide (FUGESI) as a metal gate in pFETs. Using HfSiON dielectrics and comparing to Ni FUSI devices, we demonstrate that the addition of Ge in poly-Si gate results in 1) Fermi-level unpinning with >200 mV increase in work function; 2) improved dielectrics integrity: such as decreased 1/f and generation-recombination noise, improved...
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