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Markov sources have been shown to be efficient pseudo-random pattern generators in SCAN-BIST. In this paper we give a new design for Markov sources. The new design first reduces the ATPG test set by removing the test cubes with low sampling probability and then produces test sequences based on a unique dynamic transition selection technique. Dynamic transition selection offers four transition options...
Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed...
For volume production of VLSI designs in future technologies fast and accurate diagnosis of manufacturing defects on a large number of chips is necessary to ramp up yields. Methods to speed up commonly used effect-cause fault diagnosis procedures have been recently proposed. These include the use of fault response dictionary. However, for very large industrial designs, these methods either need very...
Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that...
The path delay fault coverage achievable for a circuit may be low even when enhanced scan is available and only faults associated with critical paths are considered. To address this issue we describe a design-for-testability (DFT) approach that targets the critical (or longest) paths of the circuit. In a basic step of the proposed procedure, a fanout branch that is not on a longest path is disconnected...
The peak power dissipated in nonscan logic during fast capture cycles of scan-based two-pattern tests for path delay faults is considered. It is first demonstrated that the peak-power dissipation for an enhanced-scan test set, which has the smallest peak-power dissipation, is lower than that for a skewed-load test set and that the peak-power dissipation for a skewed-load test set, which has the smallest...
In this paper we present a new technique to speed up the effect-cause defect diagnosis by using a dictionary of very small size. In the proposed method, a dictionary of small size is used to reduce the number of events (gate evaluations) during the simulation of failing patterns and also a procedure to select a subset of passing patterns for simulation. Although the dictionary size is smaller, experimental...
In this paper the authors address the problem of reducing the energy consumption in distributed embedded systems associated with time-constraints and equipped with fault-tolerant techniques. A greedy heuristic is presented to reduce the energy during task mapping and fault tolerance policy assignment. Fault tolerance is achieved through task re-execution and replication. The proposed approach can...
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