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Electromigration (EM) is considered to be one of the most important reliability issues for current and future ICs in 10nm technology and below. In this paper we focus on the EM stress evaluation for one-dimensional multi-segment interconnect wires in which all the segments have the same direction, which is a common routing structure for power grid networks. The proposed method, which is based on integral...
Detailed routing is an important stage in VLSI physical design. Due to the high routing complexity, it is difficult for existing routing methods to guarantee total completion without design rule checking violations (DRCs) and it generally takes several days for designers to fix remaining DRC-s. Studies has shown that the low routing quality partly results from non-optimal net-ordering nature of traditional...
With the rapid growth of design size and complexity, global routing has always been a hard problem. Several new factors contribute to global routing congestion and can only be measured and optimized in 3-D global routing rather than 2-D routing. We propose an enhanced congestion model in global routing to capture local congestion and more accurately reflect modern design rule requirements. To achieve...
To capture detailed routing congestion factors in sub-90nm technology nodes, we propose a practical congestion model embedded in 3-D global routing grid graph. Using a concept of pass-through capacity and demand, intra-gcell congestion contributed by fat vias, stacked vias, local nets and related design rules can be measured and optimized. Proposed congestion model is compatible with existing widely-used...
As the number of on die transistors continues to increase, whether it is possible to generate a near optimum P/G grid automatically in early design stage will significantly affects design closure. In this paper, optimal conditions for P/G grid automatic generation are discussed. We prove that for regular grid, there does not exist a global optimal point at which both metal usage and maximal voltage...
The phase of resource allocation is always ignored in analog routers, since the small scale of analog integrated circuits does not require it. However, in this paper, we introduce a novel resource allocation algorithm, for the traditional greedy strategy without resource allocation cannot meet many performance requirements of analog integrated circuits at all. This algorithm is based on the probabilistic...
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