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This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower...
A fully integrated 79-to-87GHz cascading frequency synthesizer, which combines a W-band push-push ×4 frequency multiplier and a K-band divider-less fundamental PLL with sampling phase detector, is implemented in a standard 65nm CMOS process. It consumes low power of 54mW, achieves as low as −100.1dBc/Hz @ 100kHz and −106.2dBc/Hz @ 1MHz phase noise performance at divide-by-2 frequency, covers 9.6%...
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 ??s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency...
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