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This paper describes and analyzes a low power and high speed differential comparator. The designed comparator is intended to be implemented in a 10bit 20MHz pipeline analog-to-digital converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The offset voltage of the designed comparator has been reduced by means...
A low phase noise and highly tunable 5.15-GHz LC VCO is presented and analyzed. The phase noise achieved is -97 and -118 dBc/Hz at 100 KHz and 1 MHz offsets respectively from the carrier frequency of 5.15 GHz, with 2.5 V power supply voltage and giving a low power consumption of 11.4 mW by considering the proposed oscillator topology, which exhibits less power consumption than the traditional VCO...
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