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The next-generation cloud computing systems are expected to be connected to the real world more tightly by massive amounts of sensors and actuators. Today's clouds, however, are not capable of handling massive sensor data or giving fast feedback to the real world because of the long latency and limited bandwidth of WANs. We propose a cloud architecture that allows fast response to the real world in...
This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC)...
A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP...
A full-custom learning processor architecture has been developed based on the K-means algorithm aiming at realtime clustering applications. In order to accelerate the convergence and improve the quality of solutions, an automatic initial seeds generation function has been implemented in the architecture. The concept has been verified by the measurement of the proof-of-concept chip designed and fabricated...
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation...
A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has...
A self-controllable-voltage-level (SVL) circuit--which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode--was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories...
A new DC/DC level converter has been developed for use in high-speed, low-power circuits. The level converter can increase the DC voltage which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-µm HEMT technology to examine the effectiveness of the DC/DC level...
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