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A 125 MHz 1 GIPS at 1.3 V 1 W microprocessor with single-chip tightly-coupled multiprocessor architecture and low-voltage circuits is targeted to high-performance and low-power embedded systems, especially smart information terminals. This paper shows an entire chip diagram integrating four tightly-coupled processors. Each processing element (PE) is in-order two-way issue superscalar with two ALU...
This paper first outlines a broad range of reconfigurable computing research activities from a perspective of system LSI designs. Then, the paper focuses onto dynamically reconfigurable logic (DRL) LSI, a prototype chip that we developed to evaluate the reconfigurable computing concept. Through its ability to exchange hardware contexts quickly, this chip can accelerate media/communication applications...
The authors discuss progress achieved in the development of dedicated programmable real-time video signal processors (VSPs) for video data coding/decoding and of new technologies to improve VSP performance. A number of VSP LSIs are introduced, including a 14.5 MHz 16 bit Programmable Video Signal Processor (P-VSP), a 200 MHz 16 bit 0.8 mu m BiCMOS Super-high Speed Signal Processor (SSSP), a 250 MHz...
A 200-MHz, 600-MOPS, 16-bit, super-high-speed fixed-point BiCMOS DSP (digital signal processor) has been developed for video signal processing, including discrete cosine transforms (DCTs) for picture coding. A block diagram is shown of the processor, which consists of a 16-bit binary adder, a 16-bit*16-bit redundant binary multiplier (RB-MPY), and a 35-digit RB accumulator (RB-ACC). The RB-MPY is...
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