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Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The...
Time Dependent Dielectric Breakdown (TDDB) in p-FETs with HfSiON/SiO2 gate stacks under negative bias stress has been studied. It is shown that the shape parameter of Weibull distribution of Tbd, β, is very small value independent of gate electrode materials. This small β seems to arise from the interface layer (I.L.) breakdown. Further experimental result reveals the existence of additional interface...
The dielectric degradation under electrical stress application was attributed to generation of oxygen vacancy, and structural transformation in HfSiON films, in addition to widely known charge trapping. The former two result from ion drift under electrical field due to its ionic character of Hf-based dielectrics. While Vo generation and charge trapping are atomic-range phenomena, it is surprising...
We have theoretically analyzed the mechanism of PBTI degradation of high-k gate dielectrics. We proposed a PBTI degradation model based on a comprehensive physical theory using the general notation of gate leakage current and adequate trap distribution. Furthermore, by taking account not only pre-existing but also stress-induced defects, our model could explain the experimental data with high accuracy...
We investigated in detail the relationship between the 1/f noise, carrier mobility and interface state defects between the Si substrate and oxide on (110) and (100) substrates. In the case of pMOSFETs, the 1/f noise is independent of the mobility degradation due to the increase of effective hole mass in Si channel. However, the 1/f noise is strongly related to the degradation in the hole mobility...
We report dynamic and microscopic investigations of electrical stress induced defects in a high-k/metal gate stack by electron beam induced current (EBIC). The correlation between dielectric breakdown and EBIC sites are reported. A systematic study was performed on pre-existing and electrical stress induced defects. These defects are successfully visualized. The origin of pre-existing defects is discussed,...
We have clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB). Although La incorporation is effective for pre-existing defect suppression, stress induced defect generation is more sensitive to stress voltage and temperature. This is caused by the elevation of the energy level of oxygen vacancy and high ionicity of La-O bond. The origin of defects...
Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and...
We have clarified the difference in NBTI and 1/f noise of high-k/metal gate pMOSFETs between (110) and (100) oriented surfaces. Although the initial interface state density on (110) is higher than that on (100), the NBTI is better on the (110) surface. That is due to the different interface defect nature of interface defect states on (110) surface compared to (100). This difference has a strong impact...
We clarified the impact of the fifth material incorporation into HfSiON technology for Vth control on the reliability of high-k/metal gate stacks CMOSFETs. HfMgSiON is remarkably effective for suppressing electron traps, giving rise to a dramatic PBTI lifetime improvement for nMOSFETs. With pMOSFETs, Al incorporation is effective for the thermal deactivation of hole traps, resulting in NBTI lifetime...
We have investigated the time dependent dielectric breakdown (TDDB) characteristics for a high-k/metal gate pMOSFET under inversion stress. We found that electrons, injected from the cathode, being minority carriers in the gate leakage current play an important role in determining TDDB lifetime and found that the presence of oxygen vacancies in HfSiON determine the electron current mechanism in HfSiON...
Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. Carrier separated EBIC measurement has found that in non-stressed samples, hole conduction in pMOS is significantly enhanced by trap-assisted tunneling, while electron conduction in nMOS is independent of traps. The transport mechanisms of electron and...
This study aims to investigate the application of a technique to separate bulk hole trap effects from interface state degradation in NBTI to understand hole traps behavior including MOSFET fabrication process dependence. A gate last process is used to fabricate the pMOSFETs with HfSiON/TiN gate stacks. Results show that RTA is an effective method for reducing pre-existing hole traps, while nitridation...
We have proposed a single metal/dual high-k (SMDH), low-Vth gate stack for aggressively scaled CMISFETs. The Vth is controlled by MgO- and Al2O3-containing high-k for n and pMISFETs, respectively. The gate profile can be more easily controlled by taking advantage of a common W/TiN gate stack on both high-k's. We have successfully obtained 0.21 and -0.33 V of Vth for a 1-mum long n and pMISFET by the...
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