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A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-VT NMOS preamplifier and a cross-coupled high-VT PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-VT CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved...
The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result...
Limitations and challenges of FD-SOI MOSFETs are investigated in terms of intra- and inter-die Vt-variations, and capabilities of the body-bias control and multi-Vt MOSFETs. State-of-the-art planar FD-SOI MOSFETs are described, citing the SOTB (silicon on thin box) MOSFET as an example. FinFETs are also discussed; their challenges are clarified, and some solutions are proposed, such as high-density...
The Vmins of logic, SRAM, and DRAM blocks were compared with a newly proposed methodology for evaluating Vmin based on speed variations, taking repair techniques into account. State-of-the-art 6T SRAM cells were then discussed in terms of Vmin and cell size. After that, many adaptive circuits and relevant technologies needed to break the 1V wall were proposed and evaluated, while taking the interconnect...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Over the last decades, the Symposium has been the premier forum for memory, putting more emphasis on seminal memory circuits rather than on record-setting performances with actually fabricated full chips, which has been the emphasis at the ISSCC. Indeed, it has been the breeding ground for DRAMs, SRAMs, flash memories, and other memories.
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as...
A planar double-gate FD-SOI is compared with the bulk CMOS in terms of low-voltage operations. It turns out that due to the small VT variation the FD-SOI is suitable for deep-sub-1 V operations with improved voltage margin of RAM cells and sense amplifiers, and reduced speed variations of logic gates
A high-speed, small-area DRAM sense amplifier with a threshold-voltage (VT) mismatch compensation function is proposed. This sense amplifier features a unique hierarchy data-line architecture with a direct sensing scheme which uses only nMOS transistors in the array, and a simple VT mismatch compensation circuitry which uses a pair of nMOS switching transistors. The layout area of the sense amplifier...
Alternatives for on-chip voltage limiters and direct sensing schemes were evaluated in terms of ease of design, voltage margins and speed. Based on these evaluations, a 0.3??m ECL 4Mb BiCMOS DRAM was designed with a simulated access time of 7.8ns. It incorporates a voltage limiter featuring connection to VCC terminals, a BiCMOS output stage and use of a band-gap reference scheme, and a direct sensing...
The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage...
The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an...
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