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An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability...
A 64 K*16-b CMOS EPROM which achieves 16-ns access time using differential sensing with a constant-bias circuit is described. A compact test sense amplifier circuit in parallel with the main sense amplifier guarantees sufficient threshold voltage shift for the programmed cell for high-speed sensing. Complementary data are programmed into the pair of FAMOS transistors, which form one memory cell. The...
A novel EPROM (erasable programmable read-only memory) cell structure with asymmetrically doped source and drain junction suitable for virtual ground array architecture is described. The asymmetric cell nature eliminates a write disturbance of the adjacent cell in the write mode. In the read mode, the cell provides higher read current and substantial soft-write lifetime as a result of the selection...
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