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We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface...
In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC...
The post integration performance of cipher cores to a reconfigurable system-on-chip is a relatively unexplored area. There is also little work done on a stream aware cipher core. This paper presents an architecture that allows a cipher core to operate on multiple cipher streams without context switching. The integration of this architecture using fast simplex links to the microblaze soft-processor...
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