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This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate...
This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20-$\mu \text{m}$ bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth...
This paper demonstrates, for the first time, a high density, low cost redistribution layer (RDL) stack-up using a novel, ultra-thin dry film photosensitive dielectric material for panel scale 2.5D glass interposers and fan-out packages. The salient features of this semi-additive process based RDL demonstrator include: (1) A two metal layer RDL structure with integration of 5 µm microvias at 20 µm...
This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 µm lines and spaces with 4-5 µm diameter photo-vias for multiple re-distribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth...
Interposer technology is becoming important to interconnect ultra-high performance ICs with ultra-high density I/Os. Silicon interposers fabricated by back-end of line (BEOL) wafer processes address these wiring density requirements, but are limited by their high cost and by their high electrical losses. Organic interposers have limitations too. Their limitations are due to their poor dimensional...
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