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Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin...
We have developed a new 3-dimensional (3D) Wafer-to-Wafer stacking technology in which each wafer was stacked one after another, using a unique Through Silicon Via (TSV) fabricated by wet etching technology and surface-micro bump on the lower wafer. Our Wafer-to-Wafer stacking method use a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This interconnection...
This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality...
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