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In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by...
In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed...
In this study, we investigate the impact of thermal annealing on the electrical characteristics of epitaxial graphene field effect transistors. Top gated devices were fabricated from graphene obtained on silicon carbide (SiC) substrate. Thanks to an annealing at 300°C, the performance of the devices was enhanced by a factor of 90. The maximal transconductance reached really high values such as 5900μS/μm...
Low-field mobility in ultra-short nanotransistors is attracting large interest as strongly influenced by the role of quasi-ballistic carriers. Short-channel Silicon nanowire transistors (SiNWTs) are major candidates to work in this transport regime. Moreover, they are also expected to be strongly influenced by potential fluctuations arising from surface roughness (SR) at the Si-oxide interface. Here,...
For the first time, using a new quasi-ballistic extraction methodology dedicated to low longitudinal field conditions, experimental carrier mean-tree-paths have been determined on strained and unstrained n-FDSOI devices with Si film thickness down to 2.5 nm, gate length down to 30 nm and a TiN/HfO2 gate stack. Through deep .inversion charge and temperature investigations, dominant carrier transport...
For the first time, we report ultra-thin fully depleted silicon-on-insulator MOS transistors with WSix metal gate on HfO gate dielectric down to 40nm gate length. Gate work function, short channel performance and carrier mobility are presented and compared to TiN gate devices. Higher mobility values are obtained with a WSix metal gate device in comparison with a TiN metal gate transistor
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