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A novel switching power loss estimation method for modular multilevel converters (MMCs) with the nearest level modulation (NLM) is introduced in this paper. It focuses on the switching actions caused only by change of the inserted submodule (SM) number per arm, named as the essential switching transitions. Every essential switching action can be identified under the assumption of ideal sinusoidal...
Pseudo-differential circuits approximate the performance of fully-differential structures, while allowing single-ended operation of the two half stages in the circuit. This requires duplication of the circuitry, with accurate symmetry needed between the two halves to cancel common-mode noise. This paper proposes a single-ended scheme which uses double sampling and time interleaving to achieve a performance...
Integrated sensor interface circuits require power-efficient high-accuracy data converters. Incremental A/D converters (IADCs) are often the best choice for these, since they can provide excellent energy efficiency, and are easily multiplexed, need only simple digital filtering, and allow low latency. By performing the conversion in multiple steps, the hardware can also be multiplexed among all steps...
Integrated sensor interface circuits require power-efficient high-accuracy data converters. Incremental A/D converters (IADCs) are often the best choice for these, since they can provide excellent energy efficiency, and are easily multiplexed, need only simple digital filtering, and allow low latency. By performing the conversion in multiple steps, the hardware can also be multiplexed among all steps...
Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is the incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of single- and multi-stage IADCs. By using a direct-input feed-forward modulator, the IADC accumulates the residue voltage, and it is easy to implement...
With worldwide deployment of 100Gbps coherent DP-QPSK, beyond 100G optical communication technology, which is featured by high-order modulation, spectral compression, flex grid, and super-channel, has become one focus of industry. The new features of physical interface lead new challenge on the system performance test and evaluation. Based on the discussion of test results of two kinds of typical...
Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the...
A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and...
A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an Nth-order IADC. The implemented third-order IADC achieves a measured dynamic range of 99.8 dB and an SNDR of 91 dB for a maximum input 2.2 VPP and 250...
A low-power low-distortion ΔΣ ADC topology with shifted loop delays is proposed. Compared to the conventional low-distortion modulator, this topology can relax the critical timing for quantization and DEM by shifting the loop delay from the last integrator to the feedback path. Also, by adding one more feedback path, the last integrator can achieve both integration and active summation. Noise-coupled...
Double sampling for delta-sigma ADCs is an effective technique for wideband and low-power data conversion. This paper proposes a double-sampled delta-sigma modulator topology with shifted loop delays. Compared with existing double-sampled modulators, this architecture implements the inherent quantization delay by shifting the delay from the last integrator to the quantizer, and it relaxes critical...
A 3rd-order continuous-time ΔΣ modulator with a highly-digital technique for excess loop delay (ELD) compensation is reported. A digitally controlled reference switching matrix is used to replace the commonly used power-hungry signal adder and extra DAC driving the quantizer. The feedback DAC is embedded in the quantizer, and implemented by a few switches. The proposed technique helps the modulator...
We present a 30 GHz silicon photonic platform that includes low-loss passive components as well as high-speed modulators and photodetectors. The platform is available to the community as part of the OpSIS-IME MPW service.
We report on several multi-project wafer (MPW) platforms for optoelectronic systems, which support monolithic integration of modulators and detectors at 25 Gb/s or higher. We also describe the Luxtera platform, which includes CMOS integration.
This paper presents a single-inductor dual-output (SIDO) boost DC-DC converter with an adaptive freewheel switching technique. Due to the adoption of freewheel switching duration averaging, the optimal freewheel durations in each phase of the SIDO converter are acquired within one switching cycle. The optimal freewheel switching duration improves the efficiency of the SIDO converter, especially during...
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