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This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction...
This paper presents and evaluates a hybrid fault tolerance approach for dynamically scheduled processors that combines on-line error-correction for run-time fault handling with reconfiguration techniques for permanent fault handling. A permanent reconfiguration is triggered on-demand during runtime, depending on the frequency of on-line corrected faults. The presented work evaluates the effect of...
This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes...
Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with...
In this paper we evaluate the feasibility of software-based repair for program (NOR flash) memories in tiny embedded systems. Often, in such systems, it is very typical that not the full memory area is used by the application. This paper proposes a software-based self-repair for program memories which utilizes this inherently available redundancy. Our techniques combine application adaptation in respect...
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