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A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability...
A method to characterize distributions of read and write margins of an SRAM array using tunable ring oscillators (ROs) is presented. A 45nm CMOS testchip demonstrates a write RO with frequency that correlates well with static wordline write-trip voltage and a read RO that that correlates well with the static-current noise margin as well as with the cell read current.
Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768 Kb 45 nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and IW measurements in small on-chip SRAM macros...
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