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A new approach for fracture characterization of a particular case study on silicon die crack is presented. It consists of four phases — visual inspection, molecular dynamics, finite element method and experiment. This work aims to use these techniques to investigate and provide a theoretical explanation and analysis of the physical failure modes and mechanisms involved, from the molecular to package...
This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO2 layer effect, zero-stress temperature, single and array vias, through...
As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes...
A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism...
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