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A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, and a control unit dynamically changes frequency, voltage, and body bias for optimum performance and energy efficiency. Fast response to droops and temperature changes is enabled by a multi-PLL clocking unit and on-chip body bias. Adaptive techniques are also used to compensate...
Careful partitioning of signal-processing tasks between the analog and digital domains to exploit the strengths of each results in an efficient design of a 2B1Q ISDN basic-rate U-interface single-chip transceiver. This 5-V CMOS device provides transmission across the digital subscriber line at 160 kb/s full duplex, in full compliance with ANSI standard T1.601. The serial 2B+D data from the digital...
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