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Coupling interference from adjacent cells of conventional floating gate structure has become a main limiting factor of the scalability of NAND-type flash memory (J. Lee et al., 2002). The better immunity against the interference issue is always considered as the advantage of nitride-storage flash memory, which has been another mainstream of non-volatile memory because of its easy integration and the...
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the Vt shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension...
It is the first time to disclose that the similar interference from adjacent wordlines as found in floating-gate flash memory also exists in nitride-based flash memory. For sub-60nm nitride-based flash technologies, this interference effect cannot be ignored any more and should be well taken into consideration when defining the operation window of the memory products.
Charge profiling methodology, re-building the localized charge profile of NBit cell in TCAD environment by comparing ID-V G and GIDL curves, is exercised to disclose the distributions of injected electrons and holes after P/E cycle. The mismatch between the profiles of electrons and holes is actually observed. Besides, the difference of injected electrons between long and short channel devices are...
The stress effect on the ONO stack layer in a two-bit SONOS-type memory cell is investigated. Our results show that P/E cycles induced stress will generate extra nitride, oxide, and interface traps in the ONO stack layer. Besides, these stress created traps are unstable and will be annealed by additional thermal treatment. Storage electrons escape from stress-created nitride and oxide traps and the...
In this paper, two NAND-type PHINES flash memory architectures (1 bit/cell and physically 2 bit/cell) are proposed for mass storage applications. PHINES nitride trapping storage flash memory features high storage density, low power operation, good reliability, simple process, and high programming throughput. Fifteen-nm generation is feasible for future flash memory technology
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