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The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO's) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin is...
Problems and possible solutions to implement high-speed logic VLSI's with advanced CMOS/BiCMOS technology are discussed. The technology trend is summarized first in conjunction with its impact on the circuit designs. The paper covers BiCMOS circuit designs and other basic high-speed circuit techniques including gate sizing, dynamic/reduced swing circuits, interconnect/clock delay, and on-chip memory...
The authors describe a high-voltage layout usable for output drivers in a standard 5-V CMOS process. These outputs are useful for applications such as vacuum fluorescent displays, motor drivers, automotive equipment. There is no modification of the manufacturing process or additional masking layers needed. An application of this technique to a mux liquid-crystal-display (LCD) driver is also described
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