The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Summary form only given. The energy efficiency of electronic circuits has dramatically improved over the past two decades. At the same time, computation, storage, and communication demands continue to grow with emerging wireless multimedia devices. In this inaugural Plenary Technology-Roundtable event, experts will discuss the opportunities to achieve the next order-of-magnitude reduction in energy...
New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type...
Clock skew is a major cause of severe timing yield degradation for sub-/near-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring...
In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments...
In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.