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This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate...
A pure CMOS one-time programmable memory (PCOP) macro using a PMOS antifuse is designed for field programming. In this work, a temperature-controlled programming voltage generator (TVG) realizes field programming by improving programming characteristics over a wide temperature range, from -40?? C to 125?? C, and supply voltage variations of ??10%. In addition, the memory cell dimensions are optimized...
This paper proposes an on-chip differential transmission line interconnect using a pre-emphasis technique for high-speed onchip signaling. The new transmitter with dynamic output-impedance control for pre-distortion of signals is presented. Simulation results showed that the proposed interconnect in 90 nm Si CMOS has possibilities of over-20-Gbps signaling and better energy-per-bit performances than...
This paper proposes a high energy-efficient pulsed-current-mode transmission line interconnect (PTLI) for on-chip networks. The stacked-switch transmitter (Tx) is introduced for saving a static power of Tx. Point-to-point and multi-drop PTLIs are demonstrated, and simulation results show that the 5-mm-long PTLI with six Txs and six receivers (Rxs) can achieve multi-drop signaling. The point-to-point...
This paper presents a CMOS voltage controlled oscillator (VCO) with a high-Q inductor fabricated by using a commercial wafer-level-package (WLP) technology. A new topology suitable for CMOS VCOs with high-Q WLP inductors is proposed. Measured Q of a WLP inductor is 40 in differential mode at around 1.9 GHz. A phase noise is -134.4 dBc/Hz at a 1 MHz offset for 1.9 GHz carrier frequency, and a FoM is...
This paper proposes a low-power on-chip transmission line interconnect (TLI) using wafer level package (WLP) technology. A 0.18 mum Si CMOS process was used to fabricate a transmitter (Tx) and a receiver (Rx). The prototype TLI with a transmission line in WLP has about 40% smaller power consumption than that with a transmission line in multilevel interconnects.
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