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We have investigated a fully depleted double-gate 1-T DRAM cell device which has SONOS type storage node on control gate for nonvolatile memory function. Due to enlarged hole capacity by the large storage node and source/drain junction depth control in the floating body, we could improving data retention time, Is,(write"1")/Is,(write"0") and device scalability. Proposed device...
By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure...
In this paper, the authors proposed a new double-gate 1-T DRAM cell device which has nonvolatile memory function on one gate. Due to enlarged hole capacity in the floating body by the nonvolatile function, high write1 and low write0 current (high ??Vth) could be done. By adopting non-overlap structure, device scalability was improved. Proposed device could be a very promising candidate for a future...
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