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Low-temperature silver sintering technology, which has been proven to be a promising die-attach solution, was extended to bonding large substrates. Strong bonding strengths for substrates greater than 25 mm × 50 mm were achieved by sintering a nanosilver paste at temperatures below 270°C with less than 5 MPa pressure. To characterize thermal performance of the substrate-attach interface, we applied...
This paper describes the process development of TSV integration with 20nm CMOS technology and device performance characterization for 3D integrated circuit (3DIC) enablement. 6×55um Through-silicon-via (TSV) on 20nm CMOS technology has been developed and demonstrated. Key module process issues, such as V0 high resistance, M1 high leakage and Cu pumping which prevent TSV to be integrated with BEOL...
This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.
Self-assembled monolayer (SAM) of alkane-thiol is applied on Cu damascene structures with the aim to protect the surface against contamination and oxidation prior to bonding. Three-dimensional interconnects are realized with bumpless Cu-to-Cu thermocompression bonding by wafer-on-wafer stacking. Based on cross-bar Kelvin structure measurements, up to a 17.3% reduction in the contact resistance of...
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